Recent technological advances in the semiconductor industry have permitted highly functional, high-density circuit arrangements for integrated circuits, microprocessors and other semiconductor device applications. A by-product of such high functionality and high density is an increased demand for products employing these devices for use in numerous applications. As the use of these devices has become more prevalent, the demand for faster operation and better reliability of the devices has also increased. In addition, such devices often require manufacturing processes that are highly complex and expensive.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual dies are functional, it is also important to ensure that batches of dies perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Traditionally, integrated circuits have been tested using methods including directly accessing circuitry and/or using devices within the integrated circuit to access circuitry. These testing methods are used for designing new devices as well as for debugging manufacturing processes for existing designs. Test results obtained using these testing methods are used for identifying defects in a circuit design or in a circuit manufacturing process, which in turn is used for modifying the design and/or manufacturing process. The modified designs are used for new prototypes, which are in turn tested and re-designed as needed.
Directly accessing circuitry for device testing and analysis is difficult for several reasons. For instance, in high-density circuit applications, it is difficult to accurately navigate stimulus sources to particular circuit nodes. In addition, it is sometimes necessary to destroy a portion of the die in order to access circuit nodes, such as when accessing circuitry in a conventional die via a die passivation layer. In flip chip type N dies, transistors and other circuitry are located in a very thin epitaxially grown silicon layer in a circuit side of the die, which is arranged face-down on a package substrate. Transistors and other circuitry near the circuit side are not readily accessible for testing, modification, or other purposes due to this face-down orientation. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the die.
Another particular type of semiconductor device structure that presents unique challenges to circuit analysis is silicon-on-insulator (SOI) structure, wherein circuitry is located in a thin layer of silicon formed on an insulator, such as oxide. SOI structure exhibits benefits including reduced switch capacitance that leads to faster operation. However, direct access to circuitry for analysis of SOI structure involves milling through the insulator, which can damage circuitry or other structure in the device. Such damage can alter the characteristics of the device and render analysis of the device inaccurate. In addition, the milling process can be time-consuming, difficult to control and expensive.
The difficulty, cost, and destructive aspects of existing methods for testing integrated circuits are impediments to the growth and improvement of semiconductor technologies, including those involving flip-chip structures, conventional structures and SOI structures.